module adder_ext(
        input   [31:0]  i_ext_out,
        input   [31:0]  i_rn,
        input           i_add,
        input   [ 1:0]  i_op,
        output  [31:0]  o_result
);

wire [15:0] hihalf = i_ext_out[31:16] + i_rn[31:16];
wire [15:0] lohalf = i_ext_out[15: 0] + i_rn[15: 0];
wire [31:0] whole  = i_ext_out        + i_rn       ;

assign o_result = i_add ? ( i_op == 2'b00 ? {hihalf, lohalf} : whole ) : i_ext_out ;

endmodule
